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US Patent 7697326 Reducing programming error in memory devices

Patent 7697326 was granted and assigned to Anobit Technologies on April, 2010 by the United States Patent and Trademark Office.

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Patent
Patent

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Current Assignee
Anobit Technologies
Anobit Technologies
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
7697326
Date of Patent
April 13, 2010
Patent Application Number
11995806
Date Filed
May 10, 2007
Patent Citations Received
‌
US Patent 11790989 Soft reset for multi-level programming of memory cells in non-von neumann architectures
Patent Primary Examiner
‌
David Lam
Patent abstract

A method for storing data in an array (28) of analog memory cells (32) includes defining a constellation of voltage levels (90A, 90B, 90C, 90D) to be used in storing the data. A part of the data is written to a first analog memory cell in the array by applying to the analog memory cell a first voltage level selected from the constellation. After writing the part of the data to the first analog memory cell, a second voltage level that does not belong to the constellation is read from the first analog memory cell. A modification to be made in writing to one or more of the analog memory cells in the array is determined responsively to the second voltage level, and data are written to the one or more of the analog memory cells subject to the modification.

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