Patent attributes
A method of reading a NAND flash memory device includes a cell string having a drain selection transistor, a plurality of memory cells and a source selection transistor which are in series connected to each other. The method comprises the steps of applying a first voltage to a gate of the drain selection transistor in order to turn on the drain selection transistor, applying a read voltage to a gate of a selected memory cell among the plurality of memory cells, and applying first and second pass voltages to gates of unselected memory cells of the plurality of memory cells, wherein the first pass voltage of a relatively high level is applied to the gates of the unselected memory cells which are adjacent to the selected memory cell and wherein the second pass voltage of a relatively high level is applied to the gates of the unselected memory cells which are not adjacent to the selected memory.
