Patent attributes
In a method and apparatus for reading a logic state stored in an 8 transistor memory cell (8TMC), a differential sense circuit includes a differential input circuit having a pair of differential inputs and an output. An output signal is provided at the output and is indicative of a difference between two signals received at the pair of differential inputs. The difference is in accordance with the logic state read from the 8TMC. A sense amplifier is coupled to the output, the sense amplifier being operable to amplify the output signal that is greater than a threshold and switch the output signal to a voltage level corresponding to the logic state. The difference between the two signals measurable over a configurable time period is greater than a corresponding change in any one of the two signals measured over the same period, thereby improving the performance of the 8TMC.
