US Patent 7667525 Bus switch circuit with back-gate control during power down

The bus switch with back gate control circuit includes: an NMOS transistor coupled between a first port and a second port; a PMOS transistor coupled in parallel with the NMOS transistor; a first blocking device coupled between the first port and a control node of the PMOS transistor; a second blocking device coupled between the second port and the control node of the PMOS transistor; a first pull-down device coupled to a back gate of the NMOS transistor; and a second pull-down device coupled to the back gate of the NMOS transistor, wherein the pull down device is controlled by a power supply node and the control node of the PMOS transistor.