US Patent 7663937 Semiconductor memory device

A semiconductor memory having a plurality of memory cells coupled to bit lines includes a bit line selecting circuit, a latch circuit, and a switching circuit. The bit line selecting circuit is disposed in a cell area where the memory cells are formed. The bit line selecting circuit is configured to select one of the bit lines in response to a first control signal. The latch circuit is disposed in a surrounding circuit area. The latch circuit is configured to perform a program operation or a read operation on the memory cells corresponding to the bit line selected by the bit line selecting circuit. The switching circuit is disposed in the surrounding circuit area, and is coupled between the bit line selecting circuit and the latch circuit. The switching circuit is configured to switch between the bit line selecting circuit and the latch circuit in response to a second control signal.