Is a
Patent attributes
Patent Jurisdiction
Patent Number
Date of Patent
February 2, 2010
Patent Application Number
11393050
Date Filed
March 29, 2006
Patent Citations Received
Patent Primary Examiner
Patent abstract
A method includes joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board. The low-k dielectric layer has a dielectric constant of about 3.0 or less. The solder bumps have a lead concentration of about 5% or less. A stratified underfill is formed between the die and the package substrate or printed circuit board.
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