Patent attributes
Herein described is a method of implementing one or more native NMOS antifuses in an integrated circuit. Also described is a method for programming one or more native NMOS antifuses used within a memory device. The method further comprises verifying one or more states of the one or more native NMOS antifuses after the programming has been performed. In a representative embodiment, the one or more native NMOS antifuses are implemented by blocking the implantation of a dopant into a substrate of an integrated circuit. In a representative embodiment, an integrated circuit incorporates the use of one or more native NMOS antifuses. In a representative embodiment, the integrated circuit comprises a memory device, such as a one time programmable memory.
