Patent attributes
An integrated circuitry operable in a normal and test mode has a processing circuit, an output circuit associated with the processing circuit and a storage with a plurality of memory cells. The output circuit is formed to process in normal mode an output signal of the processing circuit and to provide a processed output signal to an output terminal. The output circuit further provides in test mode a test signal as processed output signal based on a drive signal which may be supplied externally or from the processing circuit. The storage receives in test mode the test signal and performs an evaluation of a memory property of at least one memory cell of the plurality of memory cells based on the test signal, and, in response to this evaluation, to output an evaluation signal indicating the memory property of the at least one cell of the plurality of memory cells.
