US Patent 7643361 Redundancy circuit capable of reducing time for redundancy discrimination

A redundancy circuit in a semiconductor memory apparatus includes a comparison signal receiving unit to receive a plurality of comparison signals and a fuse enable signal in parallel, wherein the comparison signals are generated by comparing a plurality of row address signals to a plurality of fuse address signals; and a redundancy control signal generating unit for providing a redundancy control signal by controlling an output signal path of the comparison signal receiving unit in response to a signal level of a row address enable signal. The comparison signal receiving unit receives the plurality of the comparison signals and the fuse enable signal while the row address enable signal is activated.