US Patent 7633820 Current limit circuit and semiconductor memory device

A current limit circuit comprising: a current limit element for limiting an output current level to within a predetermined range of a limiting current and including a first PMOS transistor having a source to which a predetermined voltage is applied and a drain through which the output current is supplied; and a gate voltage generating circuit for generating a gate voltage by a feedback control such that a difference between the predetermined voltage and a gate voltage of the first PMOS transistor coincides with a threshold voltage of a second PMOS transistor having approximately the same characteristic as that of the first PMOS transistor in a state in which a predetermined current is flowing through the second PMOS transistor.