US Patent 7629212 Doped WGe to form dual metal gates

A method of fabricating a dual metal gate structures in a semiconductor device, the method comprising forming a gate dielectric layer above a semiconductor body, forming a work function adjusting layer on the dielectric gate layer in the PMOS region, depositing a tungsten germanium gate electrode layer above the work function adjusting material in the PMOS region, depositing a tungsten germanium gate electrode layer above the gate dielectric in the NMOS region annealing the semiconductor device, depositing a metal nitride barrier layer on the tungsten germanium layer, depositing a polysilicon layer over the metal nitride, patterning the polysilicon layer, the metal nitride layer, the tungsten germanium layer, work function adjusting layer and the gate dielectric layer to form a gate structure, and forming a source/drain on opposite sides of the gate structure.