US Patent 7619298 Method and apparatus for reducing parasitic capacitance

Patent 7619298 was granted and assigned to Xilinx on November, 2009 by the United States Patent and Trademark Office.

Overview Structured Data Issues Contributors Activity

Is a

Patent

Patent attributes

Current Assignee

Xilinx

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

7619298

Date of Patent

November 17, 2009

Patent Application Number

11095812

Date Filed

March 31, 2005

Patent Citations Received

‌

US Patent 11869933 Device isolator with reduced parasitic capacitance

Patent Primary Examiner

‌

Eugene Lee

Patent abstract

A method and apparatus for reducing parasitic capacitance. A P-well blocked layer is formed directly beneath a parasitic device. The P-well blocked layer significantly increases the resistance underneath the parasitic device. The resistance of the P-well blocked layer, in effect, partially disconnects the parasitic device from the ground terminal to minimize the effective capacitive impedance that is added to the total termination impedance.