Patent attributes
A serial bus data transfer system employs an interface circuit which includes a first FIFO which receives data from a serial bus and a second FIFO which outputs data to the bus. A first processor interfaces with the FIFOs and a dual-banked shared memory comprising first and second memory banks, such that data is routed between the FIFOs and the memory banks via the first processor. A second processor interfaces with the dual-banked shared memory such that data can be bidirectionally exchanged between either memory bank and the second processor. The first memory bank can be accessed and clocked by the first processor while the second memory bank is simultaneously accessed and clocked by the second processor, and vice versa, such that data can be simultaneously transferred between the FIFOs and the second processor via the dual-banked shared memory.
