Patent attributes
Memory devices are disclosed. One example of a memory device may include two layers of memory arrays each containing at least four memory cells. In particular, the memory device includes two word lines commonly shared by the two layers of the memory arrays, with the word lines coupled with the memory cells and providing gate regions of the memory cells. Additionally, a first pair of bit lines cross under the two word lines and providing source and drain regions to the first layer of the two layers of the memory arrays, and a second pair of bit lines cross over the two word lines and providing source and drain regions to the second layer of the two layers of the memory arrays. A first set of channel regions are disposed between the source and drain regions to the first layer of the two layers of the memory arrays, and a second set of channel regions are disposed between the source and drain regions to the second layer of the two layers of the memory arrays. In addition, charge storage regions are provided with each of them disposed between a corresponding word line and a corresponding channel region.
