US Patent 7587525 Power control with standby, wait, idle, and wakeup signals

An apparatus and method for conserving power in a memory information transfer system. The system may include a direct memory access (DMA) controller coupled to a memory storage device and a peripheral device. The DMA controller transfers information from the memory storage device to a buffer in the peripheral device. The DMA controller may also transfer information from the buffer in the peripheral device to the memory storage device. When the peripheral device buffer does not have to be filled or emptied by the DMA controller, the DMA controller enters a standby mode. When the peripheral device buffer is full or empty, the DMA controller exits standby mode, empties or fills the peripheral device buffer, and reenters standby mode.