US Patent 7586780 Semiconductor memory device

In a semiconductor memory device including memory cells each having two inverters connected in a cross-coupled configuration to hold High data and Low data as a pair and two access transistors, a plurality of word lines, and a plurality of bit lines, the potential of the selected one of the plurality of word lines is controlled to be lower than a potential obtained by adding up the potential of one of Low-data-holding power sources each for holding the Low data at any time other than during a read operation and the threshold voltage of each of the access transistors.