US Patent 7582934 Isolation spacer for thin SOI devices
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Patent abstract
A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.
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US Patent 07582934 Isolation spacer for thin SOI devices US Patent 7582934 Isolation spacer for thin SOI devices
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Patent Number
0758293400
Patent Number
758293400
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Official Website
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Infobox
Is a
Patent Jurisdiction
Patent Number
075829340
Date of Patent
September 1, 2009
0Patent Application Number
120408770
Date Filed
March 1, 2008
0Official Website
Patent Primary Examiner
Edits on 26 Sep, 2022
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Infobox
Is a
Patent Jurisdiction
Patent Number
075829340
Date of Patent
September 1, 2009
0Patent Application Number
120408770
Date Filed
March 1, 2008
0Official Website
Patent Primary Examiner
Edits on 18 Jun, 2022
Golden AI
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US Patent 07582934 Isolation spacer for thin SOI devices
Infobox
Is a
Patent jurisdiction
Patent number
07582934
Date of patent
September 1, 2009
Patent application number
12040877
Date Filed
March 1, 2008
Patent primary examiner
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