Patent attributes
Exemplary embodiments provide methods and structures for controlling work function values of dual metal gate electrodes for transistor devices. Specifically, the work function value of one of the PMOS and NMOS metal gate electrodes can be controlled by a reaction between stacked layers deposited on a gate dielectric material. The stacked layers can include a first-metal-containing material such as Al2O3, and/or AlN overlaid by a second-metal-containing material such as TaN, TiN, WN, MoN or their respective metals. The reaction between the stacked layers can create a metal gate material with a desired work function value ranging from about 4.35 eV to about 5.0 eV. The disclosed methods and structures can be used for CMOS transistors including MOSFET devices formed on a bulk substrate, and planar FET devices or 3-D MuGFET devices (e.g., FinFET devices) formed upon the oxide insulator of a SOI.
