US Patent 7577048 Memory interface

A double data rate memory interface circuit for transferring data between an interfacing device and double data rate memory device. The interface circuit comprises a data input for receiving a data signal from a first of those devices, and a strobe input for receiving a strobe signal from that first device. The interface circuit also comprises delay circuitry for supplying the data and strobe signals to the other device with a timing offset introduced therebetween. The delay circuitry comprises a software programmable storage medium and a digitally controllable delay element coupled to the storage medium, the delay element being arranged to control the timing offset in dependence on a delay setting programmed into that storage medium.