Patent attributes
In accordance with the principles of the invention, an integrated circuit comprises a substrate having a first FET formed on the substrate. The first FET has a first terminal coupleable to a load, a second terminal and a control terminal. The second terminal is connected to the substrate. The substrate comprises a parasitic body diode coupled between the first terminal and the substrate. The body diode is disposed such that it becomes conductive when a reverse voltage across the FET first terminal and the substrate is at least a first diode forward voltage. A voltage detector is formed on the substrate. The voltage detector has a first input coupled to the FET first terminal, a second input coupled to the substrate, and an output coupled to the FET control terminal. The voltage detector is responsive to a reverse voltage level at the FET first terminal that is less than the first diode forward voltage to turn the FET on for the duration of a reverse voltage having at least said reverse voltage level. The parasitic body diode is thereby prevented from injecting current into the substrate.
