Patent attributes
A shutter system for a pixel array is disclosed. The system includes a read shift register, first and second reset shift registers, and a plurality of logic gates. The read shift register is configured to sequentially count rows of the pixel array from top to bottom, such that the read shift register generates a read pointer. The first reset shift register is configured to sequentially reset rows of the pixel array from top to bottom. The first reset shift register provides a first reset pointer for allowing reset of pixels in a row indicated by the first reset pointer. The first reset pointer allows reset of pixels prior to reading of the pixels in a row indicated by the read pointer. The time difference between the first reset pointer and the read pointer indicates an exposure time. The second reset shift register is configured to provide a second reset pointer, which enables the first reset shift register to sequentially reset rows of the pixel array without generating any flashes when the exposure time is increased. The plurality of logic gates direct outputs of the read shift register and the first and second reset shift registers to each pixel in the pixel array.