US Patent 7564724 Flash memory device

A flash memory device includes a normal memory cell array for storing data, a normal page buffer for inputting data to the normal memory cell array or reading data stored in the normal memory cell array, one or more reference memory cell blocks for storing reference data, one or more reference page buffers for inputting reference data to the reference memory cell blocks or reading reference data from the reference memory cell blocks, and outputting a reference control signal, and one or more latch signal generators for generating first and second latch control signals supplied to the normal page buffer and the reference page buffers in response to the reference control signal. A reference bit line signal is formed using the reference memory cell block, the reference page buffer, and the latch signal generator.