US Patent 7548228 Gate driver circuit and display device having the same

The first shift register applies (4n−3)-th and (4n−2)-th gate signals to (4n−3)-th and (4n−2)-th gate lines, respectively, in response to a first clock signal, a second clock signal having a delayed phase by 1H time with respect to the first clock signal, and a third clock signal having opposite phase to the first clock signal. The second shift register applies (4n−1)-th and 4n-th gate signals to (4n−1)-th and 4n-th gate lines, respectively, in response to the first clock signal, the third clock signal, and a fourth clock signal having opposite phase to the second clock signal. Therefore, a number of transistors in the first and second shift registers may be reduced.