Patent attributes
An electrostatic discharge (ESD) protection circuit that includes a parallel connection of parasitic vertical and lateral bipolar junction transistors (BJTs) each with a floating base and a metal oxide semiconductor (MOS) field transistor with a floating body is disclosed. The three transistors may be connected in parallel between a bond (input or output) pad and a substantially fixed voltage level (e.g., a ground (or zero potential) or Vcc, depending on the transistor configuration) in a semiconductor electronic device so as to protect transistor gates or other circuit portions from damage from electrostatic voltages. The parasitic BJTs and the field transistor may be configured to remain cut off so long as an input voltage at the pad is between a negative V1 voltage (−V1) (V1>0) and a +V2 voltage (V2>Vcc), thereby allowing a greater input voltage swing without signal clamping. In one embodiment, the parasitic BJTs are PNP transistors and the field transistor is a PMOS transistor. In another embodiment, the parasitic BJTs may be NPN transistors whereas the field transistor is an NMOS transistor. The PMOS field transistor and at least the lateral PNP BJT may be configured to conduct to discharge a negative electrostatic voltage, whereas, in case of a positive electrostatic voltage, at least one of the parasitic PNP BJTs may provide a discharge path. On the other hand, an NMOS field transistor and at least one of the lateral NPN BJTs may be configured to conduct to discharge a positive electrostatic voltage, whereas, in case of a negative electrostatic voltage, at least one of the parasitic NPN BJTs may provide a discharge path. Any electronic device, including a memory device, may be configured to employ the ESD protection circuit according to the present disclosure. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
