Patent attributes
A memory device includes a matrix of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell including a transistor having a first conduction terminal, a second conduction terminal and a control terminal; a plurality of bit lines each one associated with a column, each transistor of the column having the first conduction terminal coupled with the associated bit line; a plurality of first biasing lines each one associated with a row, each transistor of the row having the control terminal coupled with the associated first biasing line; a plurality of second biasing lines each one associated with at least one row, each transistor of the at least one row having the second conduction terminal coupled with the associated second biasing line; and means for programming at least one selected memory cell belonging to a selected row. The means for programming includes first biasing means for applying a programming voltage at least to a selected first biasing line associated with the selected row, and second biasing means for applying a program enabling voltage to a selected second biasing line associated with the selected row, each memory cell being programmed only when receiving both the programming voltage and the program enabling voltage.
