US Patent 7518937 Parallel bit test circuit and method

A parallel bit test circuit for a semiconductor memory device may include a plurality of data compressors, a delay unit, and a bus width converter. The data compressors may receive data output from data lines, compress the data, and output the compressed data. The delay unit may receive a clock signal, and may generate (N−1) number of delayed clock signals from the clock signal when a burst length is a natural number equal to or more than 2. The bus width converter may receive the compressed data through M number of input terminals, divide the compressed data into N number of data sets, and serially output the N number of data sets through M/N number of output terminals in response to the clock signal and the (N−1) number of delayed clock signals, where M may be the number of bits of the data output from the data lines.