Patent attributes
Systems and methods of chip design and package implementation for attenuating noise in timing circuits, including phase-locked-loops (PLL) and delay-locked-loops (DLL), are disclosed. Embodiments of the present invention attenuate coupled noise, such as the effects of ground current surges, or power supply noise coupling through electro-static discharge (ESD) structures. In known systems, the ground supplies for the timing circuits are designed with power and ground supplies, separate from the core power and ground; although the ground supplies are connected via common VSSsubstrate, they are separated from pad ring output driver power and ground supplies. In embodiments of the present invention, the PLL or DLL and core supplies are kept separate from the output driver power and ground supplies, providing for improved systems and methods that attenuate the effects of ground current surges from chip output drivers as they switch from logic highs to logic lows.
