Patent attributes
An upper end voltage and a lower end voltage of a current detection resistor Rs are supplied, via first and second switches S1 and S2, to one end of a main capacitor Ci. A reference voltage VREF is supplied, via a third switch S3, to the other end of the main capacitor Ci. The operational amplifier OP has a negative input terminal to which a voltage of the other end of the main capacitor Ci is supplied and a positive input terminal to which the reference voltage VREF is supplied. The circuit performs an operation for charging the main capacitor Ci with a voltage corresponding to a difference between the lower end voltage and the reference voltage in a state where the first and third switches S1 and S3 are turned on and the second switch S2 is turned off. The circuit obtains a voltage applied to the other end of the main capacitor Ci which is equivalent to a sum of the reference voltage VREF and a difference between the upper end voltage and the lower end voltage in a state where the first and third switches S1 and S3 are turned off and the second switch S2 is turned on. The circuit detects a voltage difference between two ends of the current detection resistor Rs based on a value obtained by the operational amplifier OP that subtracts the reference voltage VREF from the obtained voltage.
