US Patent 7514714 Thin film power MOS transistor, apparatus, and method

A thin film power transistor includes a plurality of first doped regions over a substrate and a second doped region forming a body. At least a portion of the body is disposed between the plurality of first doped regions. The thin film power transistor also includes a gate over the substrate. The thin film power transistor further includes a dielectric layer, at least a portion of which is disposed between (i) the gate and (ii) the first and second doped regions. In addition, the thin film power transistor includes a plurality of contacts contacting the plurality of first doped regions, where the plurality of first doped regions forms a source and a drain of the thin film power transistor. The first doped regions could represent n-type regions (such as N− regions), and the second doped region could represent a p-type region (such as a P− region). The first doped regions could also represent p-type regions, and the second doped region could represent an n-type region.