Patent attributes
A method for fabricating non-volatile memory cells is provided. The method includes providing a substrate, forming a first dopant region in the substrate, forming a second dopant region in the first dopant region, growing a first isolation region over a first portion of the substrate, the first dopant region, and the second dopant region, growing a second isolation region over a second portion of the substrate, the first dopant region, and the second dopant region, defining a contact region in the second dopant region, the contact region extending between the first isolation region and the second isolation region, depositing a gate oxide layer to form a first gate dielectric atop the first isolation region and a portion of the contact region, and overlaying a gate conductive layer on top of the gate oxide layer to form a first gate conductor atop the first gate dielectric.
