US Patent 7496770 Power-efficient technique for invoking a co-processor

Various embodiments are disclosed relating to power-efficient techniques for invoking a co-processor. In an example embodiment, a computer system may include a first processor (e.g., a host processor) and a second processor (e.g., a co-processor). The first processor may instruct the second processor to perform an operation repeatedly on a data stream. The first processor may be placed in a low power state. The second processor may perform the operation repeatedly on the data stream while the first processor remains in the low-power state.