US Patent 7483317 Laminated memory having autonomically and sequentially activating operation

In a laminated memory, each of memory core layers includes a delay circuit having a period of delay time corresponding to a period of operation time of an internal memory circuit portion thereof. A memory core layer, which is input with a simultaneous operation signal, operates in response to the input operation signal. The delay circuit includes an autonomically and sequentially activating function for sending an operation signal to a next stage after the period of delay time passes.