US Patent 7482630 NAND memory arrays

A NAND memory array has a substrate, a source select gate formed on the substrate, and a drain select gate formed on the substrate. A string of floating-gate memory cells is formed on the substrate and is connected in series between the source select gate and the drain select gate. A drain contact has a head connected substantially perpendicularly to a stem. The head is aligned with the drain select gate and overlies a dielectric layer formed on the drain select gate. The stem overlies a polysilicon plug formed on the substrate. A bit line contact is in direct electrical contact with the head.