Patent attributes
A pull-up voltage circuit and method for reducing power consumption therewith are described. A pull-up voltage circuit has an inverter powered by a first supply voltage. A first p-type transistor and an n-type transistor are commonly gated to receive output from a first output node of the inverter to a first input node. A source region of the n-type transistor is coupled to a ground. A drain region of each of the first p-type transistor and the n-type transistor are commonly coupled at a second output node. A second p-type transistor has a gate coupled to the second output node. A drain region of the second p-type transistor, a source region of the first p-type transistor, and an input of the inverter are all coupled to a line. A source region of the second p-type transistor is coupled to the first supply voltage.
