Patent attributes
A method fabricating multiple wiring metals in a semiconductor device. The method includes forming a lower wiring metal on a semiconductor substrate, forming an interlayer dielectric on the lower wiring metal, and selectively removing the interlayer dielectric to form a contact dielectric film, a body dielectric film and an opening between the contact and body dielectric films. The method also includes filling the opening with low-k material, forming a capping dielectric on the contact and body dielectric films and the low-k material, forming a contact hole passing through the capping dielectric and the contact dielectric film to be connected to the lower wiring metal, and forming an upper wiring metal electrically interconnected to the lower wiring metal through the contact hole.
