US Patent 7472304 Double data rate system
Patent 7472304 was granted and assigned to Rapid Bridge on December, 2008 by the United States Patent and Trademark Office.
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Patent Inventor Names
Behnam Malekkhosravi0
Nadim Hashim Shaikli0
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Article (+320 characters)
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Patent abstract
An extendible timing architecture for an integrated circuit is disclosed. The extendible timing architecture provides metal programmable components for use with different operational clock frequencies. In some embodiments the architecture utilizes master/slave DLLs with a double data rate memory circuit.
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US Patent 07472304 Double data rate system US Patent 7472304 Double data rate system
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Patent Number
074723040
Patent Number
74723040
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Official Website
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Current Assignee
Patent Jurisdiction
Patent Number
074723040
Date of Patent
December 30, 2008
0Patent Application Number
115178380
Date Filed
August 30, 2006
0Official Website
Patent Primary Examiner
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US Patent 07472304 Double data rate system
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
07472304
Date of patent
December 30, 2008
Patent application number
11517838
Date Filed
August 30, 2006
Patent primary examiner
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