Patent attributes
A core control circuit outputs operation control signals to a memory core in order to perform refresh operations in response to an internal refresh request from a refresh request generating circuit and an external refresh request. The core control circuit sets the number of memory cells each subjected to the refresh operation in response to the external refresh request larger than the number of memory cells each subjected to the refresh operations in response to the internal refresh request. By relatively increasing the number of memory cells each subjected to the refresh operation in response to one external refresh request, the number of external refresh requests required to refresh all memory cells can be reduced. Accordingly, the frequency with which the external refresh request is supplied to the semiconductor memory can be lowered, which can improve access efficiency.
