Patent attributes
A phase locked loop (PLL), including a phase-frequency detector receiving two clock signals and outputting a phase detection signal corresponding to the phase difference between the two clock signals is provided. A controller receives the phase detection signal and generates a first control signal and a second control signal according to the phase detection signal, an oscillator receiving the first control signal and outputting a first output clock signal with a folded period corresponding to the first control signal and a loop divider receiving the second control signal and the first output clock signal dividing the frequency of the first output clock signal by an integer unfolding divisor corresponding to the second control signal and outputting a second output clock signal coupled to the phase-frequency detector. The PLL eliminates unlocked frequencies for all process imperfections, has decreased circuit area and provides a broad output bandwidth.
