Patent attributes
Disclosed is a method for testing a memory device, which can test a memory cell block while testing another memory cell block, so as to catch a process defect of the memory device within a short time period, thereby reducing the test time. The method for testing a memory device provided with a bank including N memory cell blocks and sense amplifiers, the method comprising the steps of: a) expressing the N memory cell blocks as a first, a second, . . . , an Nth memory cell block; b) sequentially activating odd-numbered memory cell blocks of the N memory cell blocks one by one in a predetermined time period; c) performing sense, read (or write) and precharge operations for each activated memory cell block; and d) performing steps a) to c) for even-numbered memory cell blocks after tests for all the odd-numbered memory cell blocks are finished.
