US Patent 7466180 Clock network

A clock network comprises a clock distribution path coupled to a circuit. The clock distribution path and the circuit are formed on a substrate. The clock distribution path comprises a plurality of interconnected elements and one or more disconnected elements. The disconnected elements can be connected to the plurality of interconnected elements after the clock distribution path is tested in connection with the circuit. In one embodiment, the disconnected elements include a capacitor, an interconnect, and a buffer. In an alternative embodiment, the plurality of interconnected elements include a buffer, an interconnect and a capacitor.