Patent attributes
There is disclosed a semiconductor integrated circuit comprising a plurality of memory macros each including a redundancy cell, each of the memory macros being assigned with an address and transferred with data of a defect address of a semiconductor memory and store the data of the defect address, a plurality of non-volatile memory elements less in number than the plurality of memory macros, each of which stores redundancy data to be transferred to a memory macro and address data showing the memory macro as a transfer destination of the redundancy data in a form of set, and a transfer control circuit which transfers the redundancy data to the memory macro as the transfer destination from the non-volatile memory elements in accordance with the address data showing the memory macro as the transfer destination.
