US Patent 7460388 Semiconductor memory device

A semiconductor memory device includes first and second global bit lines; first, second, third and fourth local bit lines; first, second, third and fourth hierarchical switches for respectively connecting the first global bit line and the first local bit line to each other, the second global bit line and the second local bit line to each other, the first global bit line and the third local bit line to each other, and the second global bit line and the fourth local bit line to each other; and first and second precharge circuits for respectively precharging the first and second global bit lines. When a memory cell connected to the first local bit line is read, the third hierarchical switch is turned off, and the first precharge circuit terminates its precharge operation after the third hierarchical switch is turned off and before a selected word line connected to the memory cell to be read is activated.