US Patent 7457175 Dual data rate memory strobe checker

A memory controller includes a gate circuit gating a data strobe signal from a memory device, a delay circuit delaying the data strobe signal from the gate circuit, a read buffer capturing values of a data signal from the memory device in response to the data strobe signal, a cumulative strobe counter incrementing a detected strobe count by the number of edges detected in the data strobe signal, and a control logic controlling the gate circuit and receiving the detected strobe count from the strobe counter. The control logic enables and disables the gate circuit after the start of a preamble and before the end of a postamble in the data strobe signal, respectively. When the memory controller is not expecting the data strobe signal from the memory device, the control logic compares the detected and the expected strobe counts and reports a strobe error when they do not match.