Patent attributes
The present invention is directed to a dual chip package that is connected to a host and includes a first memory chip and a second memory chip. Each of the first and second memory chips includes a flash memory; an option pad connected to either a first or second voltage; a register configured to store a flag signal indicating whether a memory chip is selected; a comparator circuit configured to compare a flag signal stored in the register with a logic value apparent at the option pad to generate a flash access signal. Each of the first and second memory chips also includes a memory controller unit configured to access the flash memory in response to the flash access signal, and an interrupt controller unit configured to provide an interrupt signal to the host in response to the flash access signal and a control signal provided from the host.
