Patent attributes
In a method of fabricating a semiconductor device, a liner is deposited over a conductive region of a wafer and a stencil layer is deposited over the liner. The stencil layer and the liner are etched to form a stencil pattern for a conductive layer. A second liner is deposited over exposed surfaces of the stencil pattern, and the exposed horizontal surfaces of the second liner are removed by sputtering. A low-k dielectric layer is then deposited over the wafer, and the wafer is planarized down to the stencil pattern by chemical-mechanical polishing. The stencil pattern is removed with a wet etch to form an aperture in the wafer exposing the liner and remaining portions of the second liner. Metal is deposited in the aperture, and the surface of the wafer is replanarized by chemical-mechanical polishing to produce a planar surface for additional metallization layers that may be deposited.
