US Patent 7447074 Read-only memory

An array of ROM cells, each formed of a transistor having a first drain or source region connected to a bit line connecting several transistors in a first direction, the gates of the different transistors being connected to word lines in a second direction perpendicular to the first one, the array comprising a repetition of an elementary pattern extending over three lines in each direction and comprising nine transistors arranged so that each of the lines of the elementary pattern comprises two cells, two neighboring transistors of each pattern in the first direction sharing a same second region connected to a ground line and being connected to different bit lines from a word line to the other.