Is a
Patent attributes
Patent Jurisdiction
Patent Number
Date of Patent
November 4, 2008
Patent Application Number
11801490
Date Filed
May 9, 2007
Patent Primary Examiner
Patent abstract
An embodiment of the present invention is a technique to design a DAC. A double-summed-to-zero (DSTZ) graph is created having a plurality of nodes linked by a plurality of directed branches. The DSTZ graph represents a finite state machine (FSM) that generates a sequence for a switching block used in a mismatch-shaping digital-to-analog converter (DAC). Each of the plurality of nodes represents a state in the FSM. The DSTZ graph has a total work function and a total potential energy summing to zero for a cycle traversal. A switching sequence is generated starting from a reference node in the plurality of nodes in response to an input sequence. The reference node has a zero potential energy.
Timeline
No Timeline data yet.
Further Resources
No Further Resources data yet.
