Patent attributes
A level shifter circuit. It comprises a first level shifter unit which comprises a first transistor, a second transistor, a first diode, a first capacitor, a second diode and a second capacitor. The first transistor comprises a first gate, a first source/drain and a second source/drain. The first source/drain is electrically connected to the first voltage. The second transistor comprises a second gate electrically connected to the second source/drain, a third source/drain and a fourth source/drain respectively electrically connected to the first voltage and the first gate. The first diode has a first end electrically connected to the second source/drain and a second end receiving an inverted clock pulse signal. The first and the second capacitors are respectively electrically connected to the first and the second diodes. The second diode has a first end electrically connected to the fourth source/drain and a second end receiving a clock pulse signal.