US Patent 7437500 Configurable high-speed memory interface subsystem

Patent 7437500 was granted and assigned to LSI Corporation on October, 2008 by the United States Patent and Trademark Office.

Overview Structured Data Issues Contributors Activity

Is a

Patent

Patent attributes

Current Assignee

LSI Corporation

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

7437500

Date of Patent

October 14, 2008

Patent Application Number

11198416

Date Filed

August 5, 2005

Patent Primary Examiner

‌

Sanjiv Shah

Patent abstract

A core including a write logic IP block, a read logic IP block, a master delay IP block and an address and control IP block. The write logic IP block may be configured to communicate data from a memory controller to a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The read logic IP block may be configured to communicate data from the double data rate (DDR) synchronous dynamic random access memory (SDRAM) to the memory controller. The master delay IP block may be configured to generate one or more delays for the read logic IP block. The address and control logic IP block may be configured to control the write logic IP block and the read logic IP block. The core is generally configured to couple the double data rate (DDR) synchronous dynamic random access memory (SDRAM) and the memory controller.