US Patent 7433259 Semiconductor memory device having layered bit line structure

A basic unit block has a plurality of memory cells, a local bit line pair connected to the plurality of memory cells, and a bit line precharge circuit and a transfer gate switch circuit which are connected to the local bit line pair. The local bit line pairs in a plurality of basic unit blocks are connected to a global bit line pair via the transfer gate switch circuit. The global bit line pair constitutes a layered bit line structure together with the local bit line pair. The global bit line pair is laid out to extend in the same direction and is twisted once or more in this extending direction.